Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are design generation, synthesis, placement, and routing of the system on the target device.
Modern high-end target device designs aim to support bandwidth-heavy applications. For example, current generation communications processing designs implemented on target devices support 10 Gb to 40 Gb throughput. Future designs will be targeting 100 Gb to 400 Gb and then Tb processing. Such applications are enabled by increasing speeds of transceiver serial input output) blocks which are keeping pace with the input output bandwidth needs of applications.
As target device architects create next-generation designs to support these high-bandwidth applications, and as system designers attempt to implement their systems on these target devices, tools for architecture exploration and design planning will play an important role for creating target devices and systems that successfully meet timing requirements.